Dithering is a well known technique for improving the accuracy and the digital resolution of analog-to-digital conversions. The technique of dithering involves adding a random noise signal [hereinafter dither signal] to an analog input signal before conversion of the analog input signal, and afterwards, subtracting the dither signal from the output of the conversion.
In the typical dithered analog-to-digital conversion circuit, the dither signal is generated with a digital pseudo-random noise (PRN) generator which produces a sequence of random digital values. The random digital values are converted by a digital-to-analog converter (DAC) into analog form and combined with the analog input signal at a summing junction. The combination of the analog input signal and dither signal is converted by an analog to digital converter (ADC) which produces a digital output signal. Finally, the original form of the dither signal (the sequence of random digital values) is subtracted from the digital output signal. Ideally, the digital output signal then corresponds only to the analog input signal. The path followed by the dither signal in the typical dithered analog-to-digital circuit is illustrated in block diagram form by FIG. 2.
A problem with the dithering technique occurs when subtraction of the digital dither signal from the digital output signal fails to completely remove the dither signal from the digital output signal. Any such residue of the dither signal in the digital output signal results in the digital output signal being an inaccurate digital representation of the analog input signal. One reason for the occurrence of dither signal residue is that the dither signal is amplified along the dither signal path. Amplification may occur, for example, during conversion of the dither signal by the DAC or the ADC. When this happens, the dither signal present in the digital output signal before the subtraction will be greater or less than the original, digital dither signal. Since only the digital dither signal is subtracted, a residue of the amplified dither signal remains in the digital output signal. This mismatch in gain between the dither being added in and the dither being subtracted out is known as gain error. This gain error results in increased noise which limits the signal-to-noise dynamic range of the AD circuit.
In a copending application, Ser. No. 07/817,710, filed Jan. 7, 1992, Don Hiller, a co-inventor of the present invention, disclosed a technique for correcting gain error through use of an active gain control loop. A circuit constructed according to the technique is shown in FIG. 1. The technique consists of adjusting the gain of the dither signal path according to the amount of dither signal residue remaining in the digital output signal after subtraction of the dither signal. Dither signal residue is detected by correlating the digital output signal to the digital dither signal. (In a simplified version, it is sufficient to correlate the digital output signal to only the most significant bit of the digital dither signal.) The amount of correlation corresponds to the amount of dither signal residue in the digital output signal. A signal proportional to the amount of correlation is fed back to a component with an adjustable gain in the dither signal path and used to dynamically adjust the gain of the dither signal path. When properly adjusted, there will be no amplification of the dither signal along the dither signal path and no residue caused by gain error.
The technique just described is effective for correcting first order gain drifts. However, dithered analog-to-digital conversion circuits may also suffer from second and higher order error mechanisms contributed by limitations of the circuit's components. Non-ideal characteristics of the components also cause imperfect subtraction of the digital dither signal from the digital output signal, leaving dither signal residue in the digital output signal. Such second order effects can fundamentally limit the theoretically achievable signal-to-noise dynamic range of the dithered analog-to-digital conversion circuit.
Key examples of component limitations which can result in imperfectly subtracted dither include settling speed and signal isolation. A dithered analog-to-digital conversion circuit experiences settling errors because of speed limitations of the circuit's analog components. The PRN generator operates at a fast rate to produce a sequence of random dither values which vary greatly in magnitude from one dither value to the next in the sequence. The analog circuits and components in the dither signal path may be unable to settle to the exact magnitude of the next dither value before the ADC performs an analog-to-digital conversion of its next sample from the summing junction. However, when the exact dither value is subtracted from the digital output signal, residual error introduced by incomplete settling of the analog components remains.
A second source of residual error are those errors caused by imperfect input-to-output signal isolation of components in the dither signal path [hereinafter feedthru errors]. Imperfect input-to-output signal isolation of components results in dither values leaking through with the wrong analog-to-digital conversion sample. Such misplaced dither values will also fail to subtract correctly from the digital output signal. Typically, it is the ADC, specifically a sample and hold circuit inside the ADC, which experiences imperfect input-to-output signal isolation.
The present invention is an improvement over the first order gain control technique. The present invention is directed towards the correction of second order error mechanisms such as settling error and feedthru error. The technique of the present invention also extends to the correction of higher order error mechanisms which correlate to the dither signal.
Second and higher order error mechanisms, such as settling and feedthru errors, are the result of having a remnant of previous or subsequent dither values leaking into the current conversion sample and not being subtracted out. Correction of higher order errors, therefore, can be accomplished by anticipating the amount of error contributed by a previous or subsequent dither value and subtracting it out apriori. Correction of settling errors, for example, can be accomplished by generating a correction signal proportional to the dither value which precedes the current dither value in the PRN sequence and subtracting the correction signal at the summing junction. The settling error correction signal can be generated by, concurrently with conversion of the current dither value by the DAC, converting the preceding dither value into an analog signal with a second DAC and scaling the analog signal by a proportionality constant. Similarly, feedthru errors can be corrected by generating a correction signal proportional to the dither value following the current dither value in the PRN sequence and subtracting the correction signal at the summing junction.
The correct proportionality constant to use in generating a correction signal is dependent on the particular circuit's component limitations. An adequate proportionality constant may be determined by manually presetting the proportionality constant to a fixed value which minimizes the contribution of a particular error mechanism. However, performance characteristics of the circuit components are likely to vary with temperature and time. Such variations may change the amount of residual error caused by a particular error mechanism and require a change in the proportionality constant.
In order to compensate for variations in the performance characteristics, the present invention provides a technique for dynamically setting the proportionality constant. The proportionality constant for each correction signal is dynamically adjusted with an active gain control loop. The amount of residual error contributed by a particular error mechanism is detected with a correlator and accumulator combination. The proportionality constant for the correction signal associated with the error mechanism is then adjusted accordingly to minimize the amount of error detected.
A further feature of the invention is that the error correction circuitry can be fully implemented in digital circuitry. Thus, the invention may be incorporated into a single integrated circuit for use in dithered ADC circuits.
The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.